1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a stacked BGA (ball grid array) package capable of increasing packaging density per area.
2. Description of the Related Art
As semiconductor technologies have become advanced, more highly integrated and higher performing semiconductor devices have been developed. One of the methods developed for increasing the capability of a semiconductor device is a method of stacking multiple chips or packages in a single device. These semiconductor stacking methods allow semiconductor device package density to be increased even in instances in which the sizes of the individual semiconductor devices increase or remain constant.
The stacked semiconductor device can be implemented as a chip stacked device in which bare chips, that is, non-packaged chips, are stacked, or as a package stacked device in which packaged devices are stacked after an assembling process. Because typically only the basic electrical characteristics and functionality of the chips are tested before packaging, chip stacked devices are more likely to incorporate one or more chips having incomplete functionality and/or inadequate performance. This result is problematic because the packaging process itself may be relatively expensive compared to the chip cost and good chips will likely be discarded along with the underperforming chip(s), thereby reducing the yield and increasing the cost when chip stacked devices are discarded. Package stacked devices, sometimes referred to as three-dimensional stacked semiconductor devices, typically include two or more premanufactured and tested packages arranged in a substantially vertical stack.
On the other hand, as electronic devices have become smaller and lighter, efforts have continued to reduce the size of the semiconductor chip packages incorporated in such devices. In addition, as semiconductor devices have become more highly integrated and faster, various configurations and methods have been investigated in an effort to produce economical and reliable packages. As a result of these efforts, ball grid array (BGA) packages, in which external electrical contact portions are arranged in a grid structure, were developed and have enjoyed widespread acceptance. BGA packages are advantageous in that they provide a method for coping with the increasing number of input/output pins required for the operation of highly integrated semiconductor chips while reducing the inductive component of the electrical contact portions and allowing package sizing to approach chip scale.
FIG. 1 is a cross-sectional view illustrating a conventional stacked BGA package in which an upper BGA package 120 is stacked on a lower BGA package 110. Provided on an upper surface of the lower BGA package 110 are a plurality of lands 112, arranged outside the periphery of the central chip regions, for receiving and forming electrical and mechanical connections to the connecting solder balls 122 provided on the lower surface of the upper BGA package 120. The BGA packages included in this conventional stacked BGA package structure are larger than the incorporated semiconductor chips 115, 125, making it difficult to incorporate or adapt such BGA packages into package stacked devices that more closely approximate a chip scale package (CSP) sizing. In addition, the ability to reduce the height of the conventional stacked BGA package device illustrated in FIG. 1 is hampered by the size of the solder balls 122 required to maintain a gap 127 or separation distance between the lower and upper BGA packages 110 and 120.